In data processor systems there are typically two types of data transfers. The first is the transfer of data and instructions between memories and the central processing unit (CPU), and the second involves moving data between peripheral I/O devices and memories, or between memories. Data processing systems can handle these transfers in one of two ways:
(1) The CPU can control all data transfers. This is of course necessary where data transfers into and out of the CPU are involved. PA1 (2) A DMA (direct memory access) controller can be used to control data transfers while the CPU continues to perform data processing tasks. As a result, less of the CPU's time is wasted managing data move operations. PA1 host and peripheral data transfers during local DMA transfers; PA1 dedicated pointers and counters for peripheral interrupts; PA1 dedicated pointers for host interrupts; PA1 a host interface function using DMAC hardware; PA1 powerful host commands and accessibly to all resources; and PA1 the capability to boot a stand-alone DSP from a byte-structured ROM.
While some digital signal processors include an on-chip DMA controller (also herein called a DMAC), in traditional data processor systems the DMAC is not included on the CPU chip. In addition, in traditional data processor system most components serviced by the DMAC are located off-chip vis a vis the CPU. As a result, most DMA transfers are performed over a relatively slow external bus and are thus time consuming, being limited by the speed of the DMA bus and the various bus interfaces provided by the respective peripheral devices.
Accordingly, it is a goal of the present invention to improve DMAC performance and the speed of data transfers. This goal is achieved in part by putting as many functions as possible on-chip, including memories, peripheral interfaces, and the DMA controller. The DMAC runs concurrently with the DSP core and provides for local data transfers between DSP memory mapped resources, including memories and interfaces for various input/output (I/O) peripherals, and accepts host and peripheral data transfer requests.
To achieve some of these functions, existing DMACs provide a dedicated bus for DMA transfers and respond to interrupts from peripheral I/O devices transferring data. However none of those DMACs interrupt local DMA (e.g., data transfer between memories) to handle peripheral interrupts, nor do they provide dedicated pointers and counters for peripheral interrupts. As a result, peripheral interrupts are handled less than optimally in current on-chip DMACs. Similarly, none of the existing DMACs respond to host interrupts (for data transfer requests or commands) in the middle of a local DMA operation, nor do they provide dedicated registers to make host data transfers as efficient as possible. Finally, current on-chip DMACs do not provide a host interface that allows a host to issue DSP commands, or a boot ROM to download programs and data to a stand alone DSP. Failing to integrate such host features in the DMAC means that they must be foregone or provided elsewhere at the cost of additional hardware.
It is therefore the object of the present invention to provide an on-chip DMAC that operates concurrently with the DSP core, expedites peripheral and host data transfer requests, and provides a host interface with an eye to minimizing on-chip hardware. The specific objects are to provide: